Arithmetic and logic operations in Digital Signal Processing and Processor hardware are typically performed in operational units between periods of a clock supplied to the hardware. Operational units typically receive input data at the beginning of a clock period, perform one or more operations, and have until the end of the clock period, or in other instances a multiple of a clock period, to produce an operation result. Examples of operations performed by operational units include arithmetic operations of multiplication, division, addition, and subtraction on an operand or operandi present in the input data to produce an operation result. Also, operational units may perform shifting operations on input data to normalize an operand, multiply or divide an operand by a power of two, or to logically manipulate bits contained in the input data. Flags may monitor a single bit or all of the bits of the operation result, and usually must be generated prior to the end of the clock period in which the operation result was produced. Because flags indicate conditions present in an operation result, logic for generating flags has been interposed between the operation result and the ultimate destination of the flag. However, waiting for the operation result prior to beginning to generate flag values stretches out the delay of operations which must be captured within one or more clock periods. This is particularly true when flag values depend on all bits of the operation result, therefore necessitating several stages of logic to produce a flag value. Generating flags after the operation result in a digital signal processor or a processor, may require extending the clock period, which is equivalent to reducing the clock frequency. Thus, performance and the speed of digital signal processor or processor as a whole may be adversely impacted by the necessity of accommodating long delays in operational units to generate flags.